cross-posted from: https://lemmy.ml/post/340026
This is great for moving RISC-V to mainstream. Pine64 makes great hardware.
They actually sell one already: the Pinecil with the breakout board is a tiny Risc-V board 🤫
Nice! Do you have the link?
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This is really really cool. I want to get my hands on some capable riscV board.
What is the fuss about RISC-V? Why could I want a RISC-V board over an ARM board.
ARM is owned by a company. RISC-V instruction set is open.
The ARM company is also owned by Softbank which launders blood money from Saudi royalty/oligarchs: https://www.vanityfair.com/news/2018/10/i-wouldnt-take-that-money-saudi-arabias-dirty-investments-could-be-trouble-for-softbank
Because RISC V is ope hardware.
Rather it can be, but usually it is not. The main specs are freely available, but since the design is not copyleft the actual chip designs are usually not and often even include proprietary extensions.
I agree that it’s not completely open, but having an open ISA is alteady a huge step forward.
Yes, the ISA is open as well the reference base design. You can have a closed source implementation of the open ISA.
But with a open ISA you are free from the x86 situation where only three enterprises can make chips and have some real competition. We have some of this with ARM, but as it’s a closed ISA and controlled by one enterprise, it’s not future proof.
/me counts the number of chip producing companies…
Not really more than 3 either at semi decent node sizes.
An open ISA is certainly nice if your alternatives are owned by companies that might have to sanction you in the future, but chip production is way too complicated for an open ISA to make much difference for consumers in regards to more competion (especially outside of China).
China is leading RISC-V development, and the major Chinese designs are actually open source! The Xiangshan and Alibaba designed cores, as two examples.
Other than being open source which others have already mentioned, the RISC-V instruction set is very optimized, having been developed with the full hindsight of every ISA that came before it as well as being designed for the capabilities of modern silicon, RISC-V cores have the potential to be a lot more efficient than any of the existing dominant ISAs.
Hmm, can’t claim to be an expert, but I heard the opposite. According to the article I read the original RISC-V ISA was developed by the University of California to be simple and easy to teach, but the opposite of optimized.
By now this has surely improved a lot, but most commercially available SoCs seem to include a lot of complex out of spec and proprietary extensions to get semi decent speed. And those larger Chinese server chip designs might be ok for highly parallel workloads, but are not exactly great either (like those old AMD Bulldozer chips).
Having an open ISA like RISC-V increases competition in the market. Better for us consumers.
